1. Field of the Invention
The field of the invention is data processing, or, more specifically, methods, apparatus, and products for fencing network direct memory access (DMA) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer.
2. Description of Related Art
The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely complicated devices. Today's computers are much more sophisticated than early systems such as the EDVAC. Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input/output devices, and so on. As advances in semiconductor processing and computer architecture push the performance of the computer higher and higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that are much more powerful than just a few years ago.
Parallel computing is an area of computer technology that has experienced advances. Parallel computing is the simultaneous execution of the same application (split up and specially adapted) on multiple processors in order to obtain results faster. Parallel computing is based on the fact that the process of solving a problem usually can be divided into smaller jobs, which may be carried out simultaneously with some coordination.
Parallel computers execute parallel algorithms. A parallel algorithm can be split up to be executed a piece at a time on many different processing devices, and then put back together again at the end to get a data processing result. Some algorithms are easy to divide up into pieces. Splitting up the job of checking all of the numbers from one to a hundred thousand to see which are primes could be done, for example, by assigning a subset of the numbers to each available processor, and then putting the list of positive results back together. In this specification, the multiple processing devices that execute the individual pieces of a parallel program are referred to as ‘compute nodes.’ A parallel computer is composed of compute nodes and other processing nodes as well, including, for example, input/output (‘I/O’) nodes, and service nodes.
Parallel algorithms are valuable because it is faster to perform some kinds of large computing jobs via a parallel algorithm than it is via a serial (non-parallel) algorithm, because of the way modern processors work. It is far more difficult to construct a computer with a single fast processor than one with many slow processors with the same throughput. There are also certain theoretical limits to the potential speed of serial processors. On the other hand, every parallel algorithm has a serial part and so parallel algorithms have a saturation point. After that point adding more processors does not yield any more throughput but only increases the overhead and cost.
Parallel algorithms are designed also to optimize one more resource the data communications requirements among the nodes of a parallel computer. There are two ways parallel processors communicate, shared memory or message passing. Shared memory processing needs additional locking for the data and imposes the overhead of additional processor and bus cycles and also serializes some portion of the algorithm.
Message passing processing uses high-speed data communications networks and message buffers, but this communication adds transfer overhead on the data communications networks as well as additional memory need for message buffers and latency in the data communications among nodes. Designs of parallel computers use specially designed data communications links so that the communication overhead will be small but it is the parallel algorithm that decides the volume of the traffic.
Many data communications network architectures are used for message passing among nodes in parallel computers. Compute nodes may be organized in a network as a ‘torus’ or ‘mesh,’ for example. Also, compute nodes may be organized in a network as a tree. A torus network connects the nodes in a three-dimensional mesh with wrap around links. Every node is connected to its six neighbors through this torus network, and each node is addressed by its x,y,z coordinate in the mesh. In a tree network, the nodes typically are connected into a binary tree: each node has a parent and two children (although some nodes may only have zero children or one child, depending on the hardware configuration). In computers that use a torus and a tree network, the two networks typically are implemented independently of one another, with separate routing circuits, separate physical links, and separate message buffers.
A torus network lends itself to point to point operations, but a tree network typically is inefficient in point to point communication. A tree network, however, does provide high bandwidth and low latency for certain collective operations, message passing operations where all compute nodes participate simultaneously, such as, for example, an allgather.
One-sided message passing is a way to transmit information without active participation from a communications target, and FENCE instructions and protocols advise applications of completion of particular sequences of data communications instructions. Traditional FENCE protocols, however, are artifacts of application-level messaging modules, two-sided, inefficient, burdensome, difficult to implement. Existing FENCE protocols, for example, employ FENCE accounting with large counter arrays to guarantee the validity of FENCE operations. Readers will recognize that much of the usefulness of parallel operations, such as FENCE operations, is processing control on massively parallel machines, ‘supercomputers,’ with possibly thousands of compute nodes, millions of data communications endpoints each of which sends to all others, and therefore trillions of messages, so that such traditional FENCE accounting would require maintenance of huge counter arrays.
Parallel compute nodes, even in supercomputers, typically have limited on-board memory, so that large arrays of completion counters simply cannot scale. IBM's next-generation Blue Gene™ supercomputer, for example, supports on the order of a million communications endpoints, although each hardware process will have assigned to it only 250 MB of RAM, much too much of which would be occupied by any attempt at traditional FENCE accounting with counter arrays. Another inefficiency in traditional FENCE operations is that acknowledgement packets, even for one-sided operations, lead very quickly to excessive network congestion and poor latency even for one-sided operations, easily to be seen in a supercomputer setting with a few trillion messages in flight.